1. Field of the Invention
The present invention relates generally to a programmable logic array (hereinafter referred to as PLA) and, more specifically, it relates to a PLA in which the logic associated therewith can be arbitrarily changed.
2. Description of the Prior Art
When complicated combination logics are constituted by AND and OR gates, they require a large number of TTLs. Since a combinational logic which is relatively simple can be realized by one PLA, the application of PLA enables reduction of the number of IC packages. In addition, since the logical expressions can be directly realized, the time required for designing can be reduced. Therefore, the application of PLA is quite advantageous.
The PLA is used not only as a single IC but also in LSIs such as microprocessors. In a control portion of the microprocessor, for example, a combinational logic having a plurality of inputs and a plurality of outputs must be provided for decoding microcodes into control signals in the processors. When the logic is realized by AND/OR gates, the layout becomes irregular, and the logic diagram becomes complicated. However, when PLAs are employed, the combinational logic can be realized in a regular layout, thereby facilitating debugging, and so on.
PLAs provide a flexible and efficient way of synthesizing arbitrary combinational functions in a regular structure. The PLA circuit is based on a representation of Boolean functions as a set of sum-of-products terms. A set of such functions can be mapped into a two-stage NOR networks as shown in FIG. 1A.
FIG. 1A is a schematic diagram showing one example of a conventional PLA disclosed in, for example, Neil H. E. Weste, Kamran Eshraghian "PRINCIPLES OF CMOS VLSI DESIGN" (Addison-Wesley Publishing 1985) pp. 368.about.379, or Introduction to nMOS and CMOS VLSI Systems Design by Amar Mukherjee pp. 52.about.63. The PLA shown in this figure is so-called NOR-NOR type PLA and has three inputs (I1 to I3) and three outputs (O1 to O3) as an example. The numbers of the inputs and outputs can be arbitrarily increased by repeating the same circuit structure. Referring to the figure, the PLA comprises an AND plane for programming the AND logic and an OR plane for programming the OR logic. Input signals I1, I2 and I3 are applied to the input lines X1, X2 and X3 through inverters 1, 2 and 3. In addition, the input signal I1 is applied to an inversion input line X1 through the inverters 4 and 5, the input signal I2 is applied to the inversion input line X2 through inverters 6 and 7, and the input signal I3 is applied to the inversion input line X3 through inverters 8 and 9. Therefore, each of the input lines X1 to X3 and the inversion input lines X1 to X3 is supplied with each of the input signals I1 to I3 and the inversions thereof. Three product term lines 10 to 12 are provided orthogonal to these input lines X1 to X3 and the inversion input lines X1 to X3. These product term lines 10 to 12 are to output desired logical product of the input signals I1 to I3. Each of the P channel MOS transistors 13 to 15 is connected between one end of each of the product term lines 10 to 12 and the power supply V.sub.cc as a load. Each of the transistors 13 to 15 has its gate grounded so that it is always in the on-state, the on-resistance serving as a load. Ground lines 16, 17 and 18 are provided so as to be paired with the product term lines 10, 11 and 12, respectively. The product term lines 10, 11 and 12 extend to the OR plane respectively through the inverters 19 and 20, inverters 21 and 22 and inverters 23 and 24. These inverters 19 and 20, 21 and 22, and 23 and 24 are provided as buffers, respectively. On the OR plane, three output lines 25, 26 and 27 are provided orthogonal to the product term lines 10, 11 and 12. One end of each of these output lines 25, 26 and 27 is connected to the power supply V.sub.cc through P channel MOS transistors 28, 29 and 30, respectively. These transistors 28, 29 and 30 have their gates grounded as in the case of the aforementioned transistors 13 to 15 serving as loads. The other end of each of the output lines 25, 26 and 27 is connected to each of the inverters 31, 32 and 33, respectively. Outputs O1, O2 and O3 are provided from these inverters 31, 32 and 33. In the above described structure, programming is carried out where N channel MOS transistors 100 are arranged in FIG. 1A. The following logic will be provided by the structure of FIG. 1A: EQU O1=I1.cndot.I2+I1 EQU O2=I2.cndot.I3 EQU O3=I2.cndot.I2+I2.cndot.I3
The NOR-NOR type PLA of FIG. 1A has the logic structure of FIG. 1B, which is apparently equivalent with the AND-OR structure shown in FIG. 1C.
The programming in the PLA of FIG. 1A is effected by providing or not providing the transistor 100, and one example of the actual application is shown in FIG. 2A.
FIG. 2A shows one example of a mask layout of a PLA cell in which programming is carried out by forming or not forming thin oxide film layer 40. Referring to FIG. 2A, a thin oxide film layer 40 is formed to cover two contact holes 41 (one contact hole is connected to the product term line and the other contact hole is connected to the ground line), which are adjacent to each other with an input line X or an inversion input line X serving as a gate wiring sandwiched therebetween. Portions other than the thin oxide film layers 40 are covered with a thick oxide film. When ion implantation is carried out in this state, ions are implanted only on the surface of the semiconductor substrate below the thin oxide film layers 40, thereby forming drain regions and source regions. Consequently, transistors 100 are formed on the positions shown in FIG. 2B.
Other than the above described method, programming may be carried out utilizing aluminum wirings or utilizing the presence/absence of a contact hole. However, either of these is so-called mask program, and therefore, once the device is formed, the programmed logic cannot be changed afterwards.
Meanwhile, there is FPLA (Field Programmable Logic Array) which can be programmed after the formation of the device, in which programming is effected by melting and cutting fuse or by utilizing nonvolatile memory. However, when programming is carried out by melting and cutting fuse, once programming is effected, thereafter it cannot be changed arbitrarily. Although program can be changed when the nonvolatile memory is employed, high voltage or a special rewriting circuit is necessary for rewriting, so that the change of program cannot be carried out during the system operation. In addition, it takes much cost due to the special process.
Since a conventional PLA is structured as described above, arbitrary change of the program cannot be carried out once it is programmed and, in order to change the program, it must be thoroughly made anew from the mask. Although program can be changed in a FPLA utilizing the nonvolatile memory, the change of the program cannot be carried out during the operation of the system and, in addition, it takes much cost due to the special process employed.